The present invention relates to a semiconductor integrated circuit device and, more particularly, to a technique effective when applied to a static random access memory (i.e., SRAM).
The SRAM is accompanied by a tendency that the quantity of charge to be stored in a storage node of a memory cell is reduced to a lower value in accordance with the higher integration of the SRAM. This makes it feasible to cause the so-called "soft error" in which the stored information of the memory cell is inverted by the action of radiation such as .alpha. particles.
We therefore have proposed the following technique in the specification of U.S. patent application Ser. No. 764,208, filed on Aug. 8, 1985: a p.sup.+ -type semiconductor region is formed partially below an n.sup.+ -type source or drain region of a MISFET (i.e., Metal Insulator Semiconductor Field Effect Transistor) of a memory cell. According to this technique, a junction capacitance can be raised to increase the quantity of charge as information and to form a potential barrier thereby to prevent invasion of minority carriers established by the .alpha. particles. The p.sup.+ -type semiconductor region is formed like the source or drain region by an ion implantation using the gate electrode of the MISFET as a mask. Then, it is possible to reduce the number of the masking steps for forming the p.sup.+ -type semiconductor region and to form the same region in self-alignment with the gate.